1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to a transistor and method of making same with reduced dopant diffusion.
2. Description of Relevant Art
Fabrication of a metal-oxide-semiconductor ("MOS") transistor is well-known. Fabrication typically begins by introducing n-type or p-type impurities into a single-crystal silicon substrate. The active regions of the substrate (where the transistors will be formed) are then isolated from each other using isolation structures. In modern fabrication technologies, the isolation structures may comprise shallow trenches in the substrate filled with a dielectric such as oxide which acts as an insulator. Isolation structures may alternatively comprise, for example, locally oxidized silicon ("LOCOS") structures. A gate dielectric is then formed by oxidizing the silicon substrate. Oxidation is generally performed in a thermal oxidation furnace or, alternatively, in a rapid-thermal-anneal ("RTA") apparatus. A gate conductor is then patterned using a photolithography/etch process from a layer of polycrystalline silicon ("polysilicon") deposited upon the gate dielectric. The photolithography process allows selective removal of a photoresist film deposited entirely across the polysilicon. The portion of the photoresist film that is exposed can, according to one embodiment, be polymerized, and that which is not exposed removed during the "develop" stage of the lithography process. The regions that are non-polymerized form a mask for a subsequent etch during which portions of the polysilicon layer that are not masked by the photoresist pattern are removed. After the etch process, the patterned photoresist layer is stripped away.
The polysilicon is typically rendered conductive with the introduction of ions from an implanter or a diffusion furnace. Subsequently, source and drain regions are doped with a high-dose n-type or p-type dopant. If the source and drain regions are doped n-type, the transistor is referred to as NMOS, and if the source and drain regions are doped p-type, the transistor is referred to as PMOS. A channel region between the source and the drain is protected from the implant species by the pre-existing gate conductor. When an appropriate bias is applied to the gate of an enhancement-mode transistor, a conductive channel between the source and drain is induced and the transistor turns on.
As transistor geometries shrink below 1 micron, the limitations of conventional transistor processing become more and more apparent. As the thickness of the gate oxide decreases below 100 angstroms, devices become more susceptible to diffusion of impurities contained within the gate structure across the gate oxide and into the active area of the transistor. This problem is especially acute for gate structures into which boron is implanted. In addition, it is believed that many loosely formed bonds exist at the interface between the gate oxide and the polysilicon gate structure in conventionally formed transistors. The presence of these loosely formed bonds is believed to contribute to undesirable transistor characteristics such as susceptibility to voltage breakdown. Still further, as devices become smaller and more densely packed upon a semiconductor substrate surface, it becomes increasingly important to minimize the leakage current of each individual transistor. It is believed that leakage current can be created by a scattering effect that occurs as electrons traverse the channel between a device's source region and drain region. As the number of transistor devices within a single integrated circuit increases, leakage current can become significant enough to raise the temperature of the semiconductor substrate thereby slowing the device and, eventually, raising the temperature above the operational limit of the device. In addition, the presence of impurities in the channel of the device may cause a significant change in the threshold voltage. If the change brings the threshold outside the specification limits, the device is considered non-functional.
Therefore, it would be highly desirable to fabricate MOS transistors in a manner that reduced or eliminated diffusion from the gate transistor structure to the underlying active region of the transistor, improved the bond structure of the polysilicon-gate oxide interface, increased the source/drain drive current without a corresponding increase in leakage current, and prevented a significant change in the threshold voltage.